The present invention relates generally to discrete capacitors, and more particularly, to surface lands on the surfaces of discrete capacitors, and methods of capacitor fabrication.
Electronic circuits, and particularly computer and instrumentation circuits, have in recent years become increasingly powerful and fast. As circuit frequencies continue to escalate, with their associated high frequency transients, noise in the power and ground lines increasingly becomes a problem. To reduce such noise, capacitors known as decoupling capacitors are often used to provide a stable signal or stable supply of power to the circuitry. Capacitors are farther utilized to dampen voltage overshoot when an electronic device (e.g., a processor) is powered down, and to dampen voltage droop when the device powers up.
Decoupling capacitors and capacitors for dampening voltage overshoot or droop are generally placed as close as practical to a die load in order to increase the capacitors"" effectiveness. Often, the capacitors are surface mounted to the die side or land side of the package upon which the die is mounted. FIG. 1 illustrates a cross-section of an integrated circuit package 102 having die side capacitors 106 and land side capacitors 108 in accordance with the prior art. Die side capacitors 106 are mounted on the same side of the package as the integrated circuit die 104. In contrast, land side capacitors 108 are mounted on the opposite side of the package 102 as the die 104.
FIG. 2 illustrates an electrical circuit that simulates the electrical characteristics of the capacitors illustrated in FIG. 1. The circuit shows a die load 202, which may require capacitance or noise dampening in order to function properly. Some of the capacitance can be supplied by capacitance, as modeled by capacitor 204, located on the die. Other capacitance, however, must be provided off chip, as indicated by off-chip capacitor 206. The off-chip capacitor 206 could be, for example, the die side capacitors 106 and/or land side capacitors 108 illustrated in FIG. 1.
Naturally, off-chip capacitor 206 would be located some distance, however small, from die load 202, due to manufacturing constraints. Accordingly, some inductance, as modeled by inductor 208, exists between the die load and the off-chip capacitor 206. The value of the inductor 208 is related to the xe2x80x9cloop area,xe2x80x9d which is the electrical distance from die load 202, through capacitor 206, and back to die load 202. Because inductor 208 tends to slow the response time of off-chip capacitor 206, it is desirable to minimize the loop area, thus reducing the value of inductor 208.
Referring back to FIG. 1, die side capacitors 106 are typically mounted around the perimeter of die 104, and provide capacitance to various points on the die through traces, vias, and planes (not shown) in the package 102. Because die side capacitors 106 are mounted around the perimeter, the path length between a die load and capacitor 106 may result in a relatively high inductance feature between the die load and capacitor 106.
In contrast, land side capacitors 108 can be mounted directly below die 104, and thus directly below some die loads. However, the package also includes land side connectors (not shown), such as pins or lands. In some cases, placement of capacitors 108 on the package""s land side would interfere with these connectors. Thus, the use of land side capacitors 108 is not always an acceptable solution to the inductance problem.
FIG. 3 illustrates a top view of an eight contact discrete capacitor 300, which can be used as a decoupling capacitor or to dampen voltage overshoot or droop, in accordance with the prior art. Contacts 302 provide electrical connections to electrodes of an internal capacitor structure within capacitor 300. Going clockwise from the upper left contact 302, the polarities of contacts 302 alternate between positive and negative. This results in opposing contacts (i.e., contacts directly opposite each other) having opposite polarities. Each contact 302 includes surface lands 304 on the top surface 308 and bottom surface of capacitor 300.
Referring also to FIG. 4, which illustrates a side view of a discrete capacitor in accordance with the prior art, each top and bottom land pair is electrically connected through a side termination 402 on the side surface 404 of the capacitor. Inner electrodes (not shown) electrically connect with the side terminations 402, and thus with the surface lands 304.
The length of lands 304 is indicated by dimension 312. Generally, the land length is designed to be a length that allows a reliable, surface mount solder attachment. A ratio of the length 312 of surface lands 304 to the width 310 of capacitor 300 is typically about the same for most devices. For example, a capacitor having a width 310 of 1.3 millimeters (mm) would typically have lands 304 with lengths 312 of about 0.3 mm, which is approximately 23% of the width 310 of capacitor 300.
Capacitors sometimes have more or fewer contacts, as well. For example, FIG. 5 illustrates a top view of a ten contact discrete capacitor 500 in accordance with the prior art. Eight of contacts 502 contact the sides of capacitor 500, and are referred to herein as xe2x80x9cside contacts.xe2x80x9d Two of contacts 504 contact the ends of capacitor 500, and are referred to herein as xe2x80x9cend contacts.xe2x80x9d Going clockwise from the upper left contact 502, the polarities of contacts 502, 504 alternate between positive and negative. Unlike the capacitor illustrated in FIG. 3, this results in opposing side contacts 502 having the same polarities, while end contacts 504 have opposite polarities.
The lengths of the side and end contact surface lands are represented by dimensions 512 and 514, respectively. As with the capacitor 300 illustrated in FIG. 3, the ratio of the length 512 of the side contact surface lands to the width 510 of capacitor 500 is typically about the same (e.g., about 23%) for most capacitors. In addition, the ratio of the length 514 of the end contact surface lands to the length 516 of capacitor 500 is also typically about the same. For example, a capacitor having a length 516 of 2.0 mm would typically have end contact lands with lengths 514 of about 0.3 mm, which is approximately 15% of the length 516 of capacitor 500.
As electronic devices continue to advance, an increasing need exists for higher capacitance with reduced inductance for decoupling, voltage dampening, and supplying charge. In addition, a need exists for capacitance solutions that do not interfere with package connectors, and which do not limit the industry to certain device sizes and packing densities. Accordingly, there is a need in the art for alternative capacitance solutions in the fabrication and operation of electronic devices and their packages.